module vclkgen
		(clock, resetn, pHSYNC, dtCLK, dHSYNC, vCLK);
input			clock, resetn;
input			pHSYNC;
input			dtCLK;
output			dHSYNC;
output			vCLK;

reg			clk_half;
reg			dHSYNC;
reg			vCLK;

always @(posedge clock or negedge resetn)
begin
	if (~resetn)
	begin
		clk_half <= 0;
		dHSYNC <= 0;
		vCLK <= 0;
	end
	else
	begin
		clk_half <= ~clk_half;
		dHSYNC <= pHSYNC;
		vCLK <= ((clk_half & ~pHSYNC) | (dtCLK & pHSYNC));
	end
end
endmodule